Impact of DRAM Refresh Rate on Performance and Power

DRAM Refresh Rate

DRAM Refresh Rate is the periodic timing at which DRAM cells must be refreshed to retain data, governed by JEDEC standards and temperature. DRAM cells store charge in capacitors that leak over time; without refresh, data is lost. The rate is specified by two key parameters: tREF (maximum retention time) and tREFI (interval between refresh commands).

Core Concepts

tREF: The maximum time a cell can retain data without refresh. JEDEC requires 64ms at ≤85°C and 32ms at >85°C for most DRAM (DDR2/3/4); DDR5 uses 32ms even at ≤85°C.
tREFI: The interval between refresh commands. For 8192 rows per bank, tREFI = tREF ÷ 8192 ≈ 7.8μs (64ms) or 3.9μs (32ms).
Refresh Command: Auto-refresh (AR) or self-refresh (SR) restores charge by reactivating rows. The controller issues AR commands every tREFI to cover all rows within tREF.

Why Refresh Is Needed

DRAM cells use tiny capacitors to store binary data (charge = 1, no charge = 0). Capacitors leak charge due to semiconductor physics, so data fades over time. Refresh reads and rewrites the cell to restore charge, ensuring data integrity. Higher temperature accelerates leakage, requiring shorter tREF.

Key Timing Parameters

Parameter	Symbol	Definition	Typical Values
Retention Time	tREF	Max time per cell without refresh	64ms (≤85°C), 32ms (>85°C); DDR5: 32ms (≤85°C)
Refresh Interval	tREFI	Time between refresh commands	7.8μs (64ms/8192 rows), 3.9μs (32ms/8192 rows)
Refresh Cycle Time	tRFC	Time to refresh one row	50–200ns (varies by DRAM generation/speed)
Rows per Bank	N_rows	Number of rows to refresh per bank	8192 (common); higher density may use 16K/32K

Calculation Examples

Example 1: DDR4 at 25°C

tREF = 64ms, N_rows = 8192
tREFI = 64ms ÷ 8192 = 7.8125μs
If DRAM clock = 2000MHz (500ps per cycle):Refresh command interval (cycles) = 7.8125μs ÷ 0.5ns = 15625 cycles.

Example 2: DDR5 at 90°C

tREF = 32ms, N_rows = 8192
tREFI = 32ms ÷ 8192 = 3.90625μs
Clock = 3200MHz (312.5ps per cycle):Interval = 3.90625μs ÷ 0.3125ns = 12500 cycles.

Refresh Modes

Auto-Refresh (AR): Controller issues periodic AR commands to refresh rows sequentially. Used during normal operation.
Self-Refresh (SR): DRAM enters low-power mode with internal timer generating refreshes. Used in sleep/standby to save power.
Temperature-Compensated Refresh (TCR): Adjusts tREF based on on-chip temperature (e.g., 64ms at low temp, 32ms at high temp) for efficiency.

Impact on Performance & Power

Bandwidth Overhead: Refresh commands occupy DRAM bus time. For DDR4, refresh uses ~4.5–8% of idle time, reducing available bandwidth.
Power Consumption: Refresh is a major power draw in DRAM. More frequent refreshes (shorter tREF) increase power; TCR balances integrity and efficiency.
Scalability: Higher-density DRAM (more rows) requires more frequent refreshes or longer tRFC, increasing overhead. DDR5 optimizes with tRFCsb (short burst refresh) to mitigate this.

DDR Generations Comparison

Generation	tREF (≤85°C)	tREF (>85°C)	Key Refresh Features
DDR2/DDR3	64ms	32ms	Auto-refresh, self-refresh
DDR4	64ms	32ms	tRFC4, temperature-aware refresh
DDR5	32ms	32ms	REFab/REFsb, tRFCsb, lower tREFI

Best Practices

Follow JEDEC Timings: Use tREF = 64ms (≤85°C) for DDR2/3/4 and 32ms for DDR5 to avoid data loss.
Temperature Monitoring: Implement TCR or thermal throttling to adjust tREF dynamically.
Optimize tRFC: Use DRAM-specific tRFC values (check datasheets) to minimize refresh latency.
Burst Refresh: For high-density DRAM, use burst refresh modes (e.g., DDR5 REFab) to reduce command overhead.

Summary

DRAM refresh rate is critical for data integrity, defined by tREF (retention time) and tREFI (command interval). JEDEC mandates 64ms/32ms tREF based on temperature, with tREFI calculated by dividing tREF by the number of rows per bank. Refresh impacts bandwidth and power, so balancing compliance and efficiency is key. For specific DRAM models, always refer to the manufacturer’s datasheet for exact timing parameters.